Reference is made to U.S. Pat. No. 3,621,302 granted Nov. 16, 1971 to W. D. Pricer, entitled "Monolithic-Integrated Semiconductor Array Having Reduced Power Consumption" on application Ser. No. 791,477, filed Jan. 15, 1969 and of common assignee herewith. In U.S. Pat. No. 3,621,302, a single power source is connected to a plurality of parallel-connected storage cells, which are in one of two bistable states, to provide a common constant-current source when the cells are in a standby storage condition and to apply a constant voltage source to increase the power level when the cells are in an active condition.
Reference is made to U.S. Pat. No. 3,573,758, granted Apr. 6, 1971 to R. A. Henle and W. D. Pricer, entitled "Non-Linear Impedence Means for Transistors Connected to Each Other and to a Common Power Source" on application Ser. No. 802,927, filed Feb. 27, 1969 and of common assignee herewith. In U.S. Pat. No. 3,573,758 each of the pair of transistors of a flip-flop storage cell has its collector connected through a nonlinear impedance means to a low constant current source when the cell is in an inactive condition. The nonlinear impedance means for the conducting transistor maintains the ratio of the load impedance means to the base-emitter impedance of the conducting transistor greater than one to maintain the transistors of the cell in the desired bistable state when the transistors are connected to the low constant current source through the nonlinear impedance means.
Reference is made to U.S. Pat. No. 3,688,280, granted Aug. 29, 1972 to J. K. Ayling and R. D. Moore, entitled "Monolithic Memory System with Bi-Level Powering for Reduced Power Consumption" on application Ser. No. 74,432, filed Sept. 22, 1970 and of common assignee herewith. U.S. Pat. No. 3,688,280 discloses a monolithic integrated semiconductor circuit in which both the memory array proper and the addressing and decoding support circuitry are subjected to two power levels, i.e., a low power level when the memory array is in the non-selected or inactive state and a higher level of power necessary to render the decode and address circuitry operational and to make the lines of the array selected by said support circuitry operational for reading and writing into the memory. In order that the time required for the selection of a given line in the memory array, either a row or a column, be held to a minimum, decoding means provide an output which applies to all of the gates associated with each of the rows and/or columns, the preselected patterns required to activate a row or column during the low power or inactive state. Then, during the active state when higher power is applied, the decode circuitry functions to remove the preselected signal necessary to activate a row or column from all of the gates except the gate associated with the column or row to be activated. By functioning in this manner, the circuitry avoids a time lag when the higher level is applied which would otherwise be necessary in order to bring the preselected input signal applied to the selected gate up to the level necessary to activate the selected column or row.
Reference is made to U.S. Pat. No. 3,740,730, granted June 19, 1973 to I. T. Ho and T. S. Jen, entitled "Latchable Decoder Driver and Memory Array" on application Ser. No. 158,316 filed June 30, 1971 and of common assignee herewith. U.S. Pat. No. 3,740,730 discloses a monolithic memory comprising an array of semiconductor storage cells and a plurality of decoders for accessing information to the storage cells during a given duty cycle. Reduced power consumption is achieved by the application of addressing signals to the decoder input lines for a given time period less than the accessing duty cycle in order to attain full duty cycle activating signals on the decoder output lines for accessing the memory array, and also by virtue of the selected address input lines associated with a selected decoder not drawing current during the given time period.
Reference is made to U.S. Pat. No. 3,764,833 granted Oct. 9, 1973 to J. K. Ayling and R. D. Moore, entitled "Monolithic Memory System with Bi-Level Powering for Reduced Power Consumption" on application Ser. No. 255,897 filed May 22, 1972 and of common assignee herewith. U.S. Pat. No. 3,764,833 discloses an intermittently powered true-complement generator circuit which comprises means for intermittently applying power to said circuit and generator means for receiving a single binary signal bit input prior to the application of said power and for providing a two terminal true-complement output representative of said input only when said power is applied, said generator means providing an output in the up binary state on each of the two output terminals during periods after said signal bit is received and before power is applied.
A prerequisite for the manufacture of a highly integrated information store, or monolithic memory, is to keep the power consumption and dissipation of the storage or memory cells and the address circuits, such as the decoder and/or driver circuits, as low as possible. This is necessary because the thermal load resulting from the power intake of the store is an essential bar to higher integration densities. Therefore, in the past the art has disclosed and proposed a number of techniques for reducing the power consumption of the storage cells. To this end the supply voltage and/or the supply current, rather than being applied continuously or statically, is applied only at particular times or by way of pulses. In order to increase the integration density, it is known from the U.S. Pat. No. 3,573,758 to design the decoder circuits so that they can be pulse operated. This means that the decoder circuits are kept at a particular level only when no access is made or when reading or writing is not carried out. However, when particular storage areas are to be accessed in a given operating cycle, the input lines to the decoder drivers in accordance with this patent are raised to a necessarily high level for the whole cycle. As this operational mode of the decoder circuits is not fully adequate to reduce the power requirements as desired, U.S. Pat. No. 3,740,730 discloses a method and a circuit arrangement for operating an information store by means of which the development of heat in monolithic semiconductor stores is decreased still further. To this end latches are operated in such a manner that only during the short time required for setting the selected latches when the storage cell to be accessed is addressed, is current withdrawn from the address lines of the selected driver circuits, while in the remaining cycle time during which these latches are in their latched state the addressed storage cells are subjected to the driver currents. Although in this case the power requirements of a monolithic store are reduced still further by the latches, the solution in accordance with U.S. Pat. No. 3,740,730 is not without shortcomings. The shortcomings are: the power requirements of a highly integrated store are still too high; the cycle time is not reduced; and complicated monolithic structures are necessary for realizing the circuit arrangement.